1. Field of the Invention
This invention relates to a semiconductor device having a multi-layer wiring structure and a method of manufacturing the same, with the method comprising the steps of forming a dummy pattern for flattening an interlayer insulating film and flattening the interlayer insulating film by a chemical mechanical polishing (CMP) method.
2. Description of the Related Art
FIG. 1 is a cross-sectional view of a semiconductor device for illustrating how an inter-layer insulating film formed on a semiconductor substrate is flattened by the CMP method.
A semiconductor substrate 1 is provided with elements (not shown) formed by ion implantation and diffusion of impurities; a first inter-layer insulating film 6 formed for covering the surfaces of those elements; contact holes (not shown) formed in the insulating film 6 and connected to the elements; first layer A1 wiring patterns 7a and 7b formed on the inter-layer insulating film 6; and a second inter-layer insulating film 9.
As shown in FIG. 1, since the first layer A1 wiring patterns 7a and 7b whose films are thick are arranged on the ground of the second inter-layer insulating film 9, the surface of the insulating film 9 becomes uneven. If the second layer A1 wiring is arranged on the uneven surface of the insulating film 9, then the lithographic accuracy for wiring patterning will lower, resulting in causing various problems such as the lowering of the wiring yield and electro-migration and the weakening the resistance against physical distortion.
To avoid such problems, the surface of the insulating layer 9 should be polished and flattened with a cloth 16 using the CMP method before the formation of an A1 film for forming the second layer A1 wiring patterns. In this case, the polishing is done for both the surface of the insulating film 9 covering the area where wiring patterns are formed sparsely around the wiring pattern 7a and the surface of the insulating film 9 covering the area where wiring patterns are formed densely around each of the wiring patterns 7b simultaneously.
In this case, however, the contact pressure between the cloth 16 and the surface of the insulating film 9 covering the wiring pattern 7a becomes larger than the contact pressure between the cloth 16 and the surface of the insulating film 9 covering the wiring patterns 7b, and consequently the cloth 16 is pressed excessively against the surface of the insulating film 9 covering the wiring pattern 7a, thereby increasing the polishing rate on that portion and impairing the flatness of the surface of the insulating film 9.
In addition, when the wiring patterns 7a and 7b are formed by reactive ion etching, the etching rate for the wiring material in the densely designed area of the wiring patterns becomes higher than that for the wiring material used in the sparsely designed area of the wiring patterns. This is because the density of etching ion is equal in every unit area and the wiring material must be removed much more by etching in an area where the wiring patterns are sparsely designed than an area where the wiring patterns are densely designed. Consequently, the above method makes the etching rate for the wiring patterns vary between the densely designed wiring patterns and the sparsely designed wiring patterns.
To solve these two problems, there is a well-known technique for improving the flattening of the insulating film formed on the wiring patterns and the accuracy of wiring pattern processing by arranging in the area around the sparsely arranged wiring pattern 7a, a dummy pattern(s) not electrically connected to the wiring patterns and other elements.
FIG. 2(a) and FIG. 2(b) are a top view and a cross-sectional view, respectively, of a semiconductor device in which a dummy pattern is arranged. As shown, the dummy pattern 8 is arranged between the two first layer A1 wiring patterns 7a and 7b formed in a sparsely formed wiring pattern area. With this dummy pattern 8, the surface of the second inter-layer insulating film 9 is flattened and the second layer A1 wiring patterns 10 can be processed finely to a high degree of accuracy on the surface of the insulating film 9. Furthermore, if the wiring patterns 7a and 7b, as well as the dummay pattern 8, are formed to a density substantially the same as that of the densely designed wiring pattern area, the wiring patterns 7a and 7b can be processed accurately without causing any irregularity in etching rate when using the reactive ion etching method.
By the way, it should be noted that the surface of the insulating film 11 for passivation of the second layer A1 wiring patterns is not required to be flattened since no wiring pattern is formed thereon.
As is well known, performance speed-up and high wiring integration of semiconductor devices have been in rapid progress of late. For such a semiconductor device, an increase in wiring capacitance is becoming the main factor of hindering the performance speed-up of the target semiconductor. Thus, when forming a dummy pattern in a semiconductor device having a multiple-layer wiring structure mentioned above, it is very important not to increase the total wiring capacitance of the multiple-layer wiring structure.
Now, let us consider the inter-wiring capacitance and the inter-substrate capacitance in the structure shown in FIG. 2(a) and FIG. 2(b).
For example, compared with the structure shown in FIG. 3(a), in which only an insulating layer 19 having a thickness of T1 exists between electrodes 20a and 20b that face each other to form a capacitance, the structure shown in FIG. 3(b), in which a dielectric layer having a thickness of T2 exists in the insulating layer 19 has a capacitance of T1/(T1-T2) times that of the former. In other words, if the dielectric layer is provided in the insulating layer, the capacitance is actually equal to the capacitance when the thickness obtained by subtracting the dielectric layer thickness from the insulating layer thickness is assumed as the dummy insulating layer thickness.
Consequently, if the two electrodes 20a and 20b facing, and connected to, each other electrically and the dielectric layer 21 in the insulating layer as shown in FIG. 3(b) are assumed as dummy patterns 8 not electrically connected to the ends of the two wiring patterns 7a and 7b formed in the same wiring pattern shown in FIG. 2(a) and FIG. 2(b), then how the dummy pattern will affect the inter-wiring capacitance 18 can be found from FIG. 3(a) and FIG. 3(b) equivalently. In the same way, if the two electrodes 20a and 20b and the dielectric layer 21 in the insulating layer are assumed as dummy patterns 8 not electrically connected to the bottom of the second layer wiring pattern 10 and the surface of the substrate 1, then how the dummy pattern will affect the substrate capacitance 17 can be found from FIG. 3(a) and FIG. 3(b) equivalently.
In other words, when considering how the dummy patterns 8 will affect the inter-wiring capacitance 18, the value obtained by subtracting the width of the dummy pattern 8 inside the two wiring patterns from the interval between the ends of the two wiring patterns 7a and 7b can be assumed as the dummy thickness of the insulating film corresponding to the capacitance between two wiring patterns when the dummy pattern exists between wiring patterns. Furthermore, if two or more dummy patterns whose widths are different from each other are formed between two wiring patterns, the value obtained by subtracting the sum of the widths of the dummy patterns from the interval between the two wiring patterns can be assumed as the dummy thickness of the insulating film corresponding to the capacitance between the two wiring patterns.
In the same way, when considering how the dummy pattern 8 will affect the capacitance 17 between wiring pattern and substrate, the value obtained by subtracting the film thickness of the internal dummy pattern 8 from the total film thickness of the inter-layer insulating films 6 and 9 formed between the surface of the substrate 1 and the wiring pattern 10 can be assumed as the dummy thickness of the insulating film corresponding to the inter-substrate capacitance when the dummy pattern exists between the wiring and the substrate.
As shown in FIG. 2(a) and FIG. 2(b), therefore, if a dummy pattern is provided in an area in which wiring patterns are formed sparsely, a dummy pattern will be found between the wiring pattern 10 and the semiconductor substrate 1, so the capacitance 17 between the second wiring pattern on the dummy pattern and the substrate 1 is increased. Furthermore, since a dummy pattern 8 exists between the wiring patterns 7a and 7b, the capacitance 18 between the wiring patterns 7a and 7b is also increased.
The influence of the element separating the insulating film formed on the semiconductor substrate 1 is not taken into consideration in the above explanation. The capacitance 17 formed between the wiring 10 and the substrate 1 drops according to the thickness of the element separating insulating film in the area where the element separating insulating film is formed. However, the element separating insulating film is not formed all over the area under the wiring 10. It would be an appropriate evaluation method not to take the element separating insulating film into account if more strict design standards are to be desired.
Furthermore, if a dummy pattern is arranged on a middle layer for wiring of two or more layers, the dummy pattern, strictly speaking, will also affect items other than the wiring patterns both above and under the dummy pattern. At this time, because of two or more existing thick insulating films between layers, the influence can be ignored.
On the basis of the above discussion, the object of this invention is to provide a semiconductor device that can speed up its performance and realize high integration of wiring without increasing the total wiring capacitance of the multiple-layer wiring structure mentioned above while keeping the accuracy of wiring pattern processing by using dummy pattern(s) to secure the flattening when polishing the surface of each inter-layer insulating film of the target multiple-layer wiring structure with the CMP method.